In Peripheral Components Interface (PCI) Express architecture, flow control is a method for communicating receive buffer status from a receiver to a transmitter so as to prevent receive buffer overflow and allow transmitter compliance with ordering rules. The PCI Express specification requires a flow control (FC) update be sent at least once every 30-45 μs (microseconds). As a result, a PCI express interface and possibly other components of a computing device may exit low power/power saving states at least once every 30-45 μs to send an FC update even if there is no change in buffer status and thus no change in the FC update.
PCI Express provides the ability to support different types of traffic or Traffic Class with different levels of service through Virtual Channels. Virtual Channel 0 (VC0) provides the best effort class of service and is analogous to traditional PCI traffic. Virtual channel 1 (VC1) is added to provide guaranteed latency such as required by Isochronous traffic. Further, the PCI Express specification defines six types of FC credits (e.g. Posted Request Header, Non-Posted Request Data Payload, Completion Data Payload, etc.). Each virtual Channel maintains an independent FC credit pool. The PCI Express interfaces have been implemented with a separate periodic counter or timer for each type of FC credit. The periodic timer causes an FC update for its respective type of FC credit to be sent at least once every 30-45 μs. Due to the multiple periodic timers being driven by 10 μs clock signals, a PCI express interface and possibly other components of a computing device may actually exit low power/power saving states every 10 μs to send an FC update even if there is no change in the FC update.